MIB Viewer

dsx1SfpClkConfigClkControlSignal

OBJECT-TYPE
1.3.6.1.4.1.637.61.1.56.10.1.7
Access
read-write
Status
mandatory
Sub-identifiers
0
SEL_LOC_OR_SRC. Control signal to select the VTCXO control signal (PWM) between DPLL output and a ~4MHZ square wave signal generated dividing the same system clock. 0 Square wave generated from system clock. 1 Control signal from PLL(Phase locked loop). ALCATEL NOTE: ACCESS: RW USAGE: NA PERSIST: YES INSRVMOD: NA RANGE: 0,1 DEFVALUE: 0 UNITS: NA SPARSE: NO DESCR: NA
INTEGER { squarewave (0), pll (1) }