Each bit of this value set to '1' indicates a specific status condition in the module. Octets are numbered in the order in which they appear in the PDU. Bits are numbered from the most-significant leftmost bit in the octet (bit 0) to the least-significant rightmost bit (bit 7). Cajun numbering continues across octets, so that octet 1 bit 0 is called bit 8 in the Cajun scheme. That number is also shown below, with the octet value for each single bit set. Octet 0 high-order 4 bits show LED status. Octet 0 low-order 4 bits show ICC status. Octets 1 - 5 show power-on self test (POST) results. Cajun Octet Octet bit# bit# value Meaning 0 0/0 0x80 Media gateway red LED is on. 1 0/1 0x40 The red LED is on in one or more of the media modules. 2-3 0/2-3 Unused. 4 0/4 0x08 Integrated Communications Controller hardware watchdog alert is on. 5-7 0/5-7 Unused. 8 1/0 0x80 POST HDLC local loopback failed. 9 1/1 0x40 POST Ethernet local loopback failed. 10 1/2 0x20 POST Ethernet physical local loopback failed. 11 1/3 0x10 POST Port I/O read-write test failed. 12-15 1/4-7 Unused. 16 2/0 0x80 POST NCE0 reset failed. 17 2/1 0x40 POST NCE0 internal RAM test failed. 18 2/2 0x20 POST NCE0 FIFO loop-around failed. 19 2/3 0x10 POST NCE0 internal channel loopback failed. 20 2/4 0x08 POST NCE0 internal TDM loopback failed. 21 2/5 0x04 POST NCE0 external channel loopback failed. 22-23 2/6-7 Unused. 24 3/0 0x80 POST NCE1 reset failed. 25 3/1 0x40 POST NCE1 internal RAM test failed. 26 3/2 0x20 POST NCE1 FIFO loop-around failed. 27 3/3 0x10 POST NCE1 internal channel loopback failed. 28 3/4 0x08 POST NCE1 internal TDM loopback failed. 29 3/5 0x04 POST NCE1 external channel loopback failed. 30-31 3/6-7 Unused. 32 4/0 0x80 POST DSP reset failed. 33 4/1 0x40 POST POST SPI internal loopback failed. 34 4/2 0x20 POST Spitfire FIFO test failed. 35 4/3 0x10 POST ADC test failed. 36 4/4 0x08 POST CPLD access test failed. 37-39 4/5-7 Unused. 40-47 5/0-7 Unused.