MIB Viewer

hpevtDcnfgCpuL2Cache

TRAP-TYPE
1.3.6.1.4.1.11.2.23.35.9876
Sub-identifiers
0
An error occurred while enabling the CPU L2 shared cache. The datafield contains a 32-bit error number and 32-bits of additional error information. The CPU will be deconfigured.